[{"content":"Introduction The Kria KV260 Vision AI Starter Kit has great specs, given that the board only costs $249.00. The board has 117120 LUTs, 234240 FFs, and 23.06 Mb of on-chip memory (combining BRAM and URAM).\nThis makes the board, arguably, the most cost-effective board. For example, if we compare the LUTs per dollar, FFs per dollar, and on-chip memory per dollar, it is one of the cheapest boards out there, as it can be seen on Table 1.\nBoard Cost[$] LUTs per dollar FFs per dollar memory per dollar[Kb/$] Kria KV260 249.00 470.36 940.72 94.84 Kria KR260 349.00 335.59 671.17 67.67 ULX3S(ECP5 85F) 250.00 344.06 14.98 Tang Nano 9K 25.92 333.33 250.00 18.67 While it is one of the cheapest boards out there for what it offers, and while it offers, generally, a large amount of hardware resources, it is not a very beginner-friendly dev board1. It is alleged that Xilinx did not envision the use of Vivado(the main FPGA development tool for Xilinx\u0026rsquo;s FPGAs) with this board2. One of the reasons why the dev board is not user-friendly is that the programmable logic does not have direct access to a clock signal34. A clock signal is essential for an FPGA and the RTL(the design) that lies within it to function.\nI fixed that by designing a PCB that directly provides a clock signal to the programmable logic. The PCB exploits the Raspberry Pi camera interface connector to provide the clock signal, as can be seen in Figure 1. In this blog, I detail the Design, Validation, and Cost of this PCB, to then provide my concluding remarks in the Conclusion.\nFigure 1. Installed external clock PCB.\nDesign The KV260 dev board does not have many peripherals accessible by the programmable logic. The only high-speed peripherals are the 3 MIPI camera interfaces. One of them has a Raspberry Pi camera interface connector. That connector is the largest, making it easier (but not easy) to work with by hand. Further, that connector is an edge-connector, for which the interfacing PCB would be slotted in. This saves a connector-type component from the PCB, reducing the components required, easing soldering, and reducing the bill of materials. That is why I chose the Raspberry Pi camera interface connector to interface the PCB and provide a clock signal to the programmable logic. The Raspberry Pi camera interface uses power and logic levels of 3.3V. Because we want to feed a clock signal, it is only fitting that we use the 2 signal traces for the differential clock signal. The power and the clock signal traces are shown in Figure 2, for a Raspberry Pi Camera Module 2. The PCB design will require the same power and clock signal traces to interface with the KV260 dev board.\nFigure 2. A Raspberry Pi Camera Module 2, and its power traces and differential clock traces.\nTo send a differential clock signal, I decided to use a crystal oscillator, whose output is connected to an LVDS(low-voltage differential signaling) transceiver. The components I decided to use are respectively EPSON X1G0048010002 (Crystal Oscillator) and RUNIC RS90LV011YF5 (LVDS Transceiver), for which I included a 10nF decoupling capacitor for each of the previously mentioned components.\nThe KiCad PCB design can be found on GitHub. A KiCad view of the PCB can be seen in Figure 3.\nFigure 3. KiCad view of the PCB design file, with dimensions annotations.\nManufacturing was done by JLCPCB, while the soldering was done by me, by hand, and reenacted in Figure 5. The manufactured PCB can be found in Figure 4.\nFigure 4. PCB delivered by the manufacturer. On the left, an unpopulated PCB, and on the right, a populated PCB.\nThe PCB itself is very small and requires a steady hand to place the components. To give an idea of the size of the PCB, Figure 5 shows a reenactment of the reflow process, on a G3061 mini hot plate, which does not look so \u0026ldquo;mini\u0026rdquo; in comparison. For another point of size comparison, Figure 6 shows the PCB next to a €2 coin.\nFigure 5. Reenactment of the reflow soldering process on a G3061 mini hot plate.\nFigure 6. Size comparison of the PCB next to a €2 coin.\nAnyway, given the assembled PCB, it would be interesting to see if it actually works. The next section validates whether the PCB performs its intended function.\nValidation I do not think testing the PCB directly on the KV260 board would be a good idea, as I could damage something. Given the size of the PCB, ideally, I would have made a breakout board or some testing jig. Because I did not want to wait for the lead time of PCB manufacturing, I employed 4 hands (2 of my hands and 2 of my girlfriend\u0026rsquo;s hands) to test the PCB. My girlfriend applied power with her two hands (ground with one hand and 3.3V with the other hand). I \u0026ldquo;measured\u0026rdquo; the clock signal with my two hands (ground with one hand and the measuring probe with the other). I saw what resembled a square wave, at roughly the expected frequency (of 10MHz), roughly at the expected voltage levels (of 0V and 3.3V). This made me confident enough to test the PCB on the KV260 dev board, knowing that it would most probably not break anything.\nTo ultimately find out if the design works correctly, I inserted the PCB in its intended connector, as shown in Figure 7.\nFigure 7. Installation of the external clock PCB on the Raspberry Pi camera interface connector of the KV260 Dev Board.\nTo test whether the PCB works, I made a simple FPGA design, comprised of the files top.v and constraints.xdc, to test the correct functioning of the design. The files can be found in the reference_design folder of the GitHub repo of the PCB. But, for the convenience of the reader, the contents of top.v and constraints.xdc are included here:\ntop.v module top( input clk_p, input clk_n, output [7:0] o ); localparam Count = 10_000_000; wire clk; reg [31:0] count = 0; reg b = 1; assign o = {7\u0026#39;b0, b}; IBUFDS #( .DIFF_TERM(\u0026#34;TRUE\u0026#34;), .IBUF_LOW_PWR(\u0026#34;TRUE\u0026#34;), .IOSTANDARD(\u0026#34;DEFAULT\u0026#34;) ) IBUFDS_inst ( .O(clk), .I(clk_p), .IB(clk_n) ); always @(posedge clk) begin if (count \u0026gt; Count - 1) begin count \u0026lt;= 0; b \u0026lt;= ~b; end else begin count \u0026lt;= count + 1; end end endmodule constraints.xdc set_property PACKAGE_PIN B11 [get_ports {o[7]}] set_property PACKAGE_PIN D11 [get_ports {o[6]}] set_property PACKAGE_PIN E12 [get_ports {o[5]}] set_property PACKAGE_PIN B10 [get_ports {o[4]}] set_property PACKAGE_PIN C11 [get_ports {o[3]}] set_property PACKAGE_PIN D10 [get_ports {o[2]}] set_property PACKAGE_PIN E10 [get_ports {o[1]}] set_property PACKAGE_PIN H12 [get_ports {o[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {o[*]}] create_clock -name SysClk -period 10 -waveform {0 5} [get_ports \u0026#34;clk_p\u0026#34;]; set_property PACKAGE_PIN D7 [get_ports \u0026#34;clk_p\u0026#34;]; set_property PACKAGE_PIN D6 [get_ports \u0026#34;clk_n\u0026#34;]; set_property IOSTANDARD LVDS [get_ports \u0026#34;clk_p\u0026#34;] set_property IOSTANDARD LVDS [get_ports \u0026#34;clk_n\u0026#34;] The PCB, does indeed seem to work as intended. The system outputs the expected square wave with a period of 2 seconds, and pulse widths of 1 second, as shown in Figure 8.\nFigure 8. Validation of the clock PCB. The oscilloscope is measuring a square wave with a 2 second period, and a pulse width of 1 second. The expected, frequency divided, clock signal.\nCost The cost of the board is composed of the cost of its components, which I bought on LCSC, and the manufacturing of the PCB, done by JLCPCB. The manufacturing of the PCB does not include the cost of soldering, as I soldered the components by hand.\nDuring the manufacturing of the PCB, I received an additional charge of $6.90, on top of the original cost of $16.00(discounted to $2 by coupon) for 5 PCBs(without shipping included). The following justification was given for the additional charge of $6.90:\nWhen the stiffener area is over 100% of the FPC dimension or independent stiffeners no less than 4 pcs per board, there will be an extra cost.\nI don\u0026rsquo;t fully understand the justification of the extra charge, as I would consider the singular stiffener\u0026rsquo;s area to be 100%, but not over, the area of the FPC. Regardless, I will not count it over an idealized, amortized cost of the assembled PCB, presented in Table 2. Overall, this price makes me appreciate the cheaper and more complex, assembled PCBs sold on AliExpress and Amazon.\nItem Cost[$] Crystal Oscillator (EPSON X1G0048010002) 1.05 LVDS Transceiver (RUNIC RS90LV011YF5) 0.57 10uF capacitors x2 $0.01 x2 PCB fabrication (JLCPCB) $16.00 ÷5 Total $4.84 Conclusion The development experience, while still not great, I believe, is made much better with this PCB. What would have originally required the long and careful configuration and engineering of the Zynq through Vitis, just to obtain a clock signal, can now be done through Vivado, or through simple TCL scripts. This allows me to invest my time in the more interesting hardware design.\nWhen I started this project, I believed I could make the KV260 dev board more user-friendly and justify my possibly rash expense of $249.00, for what, on paper, seemed like a great deal. I am glad I was partially right. That said, I don\u0026rsquo;t think I would be recommending the board to a friend. This PCB alleviates some of the problems of the dev board, but I consider this work somewhat of a satirical hack, and not a serious solution.\nhttps://www.reddit.com/r/FPGA/comments/1sp6hyb/comment/oh0hedy/\u0026#160;\u0026#x21a9;\u0026#xfe0e;\nhttps://www.reddit.com/r/FPGA/comments/1sp6hyb/comment/ogzc2kh/\u0026#160;\u0026#x21a9;\u0026#xfe0e;\nhttps://adaptivesupport.amd.com/s/question/0D54U00008sOBURSA4/-info-post-pl-and-ps-clock-source-in-kria-boards-kv260kr260kd240\u0026#160;\u0026#x21a9;\u0026#xfe0e;\nhttps://adaptivesupport.amd.com/s/question/0D54U00008vA7uaSAC/kria-kv260-fpga-io-and-clock\u0026#160;\u0026#x21a9;\u0026#xfe0e;\n","permalink":"https://www.andreanardi.me/posts/adding-an-external-clock-to-the-kv260-dev-board/","summary":"\u003ch2 id=\"introduction\"\u003eIntroduction\u003c/h2\u003e\n\u003cp\u003eThe  Kria KV260 Vision AI Starter Kit has great specs, given that the board only costs $249.00. The board has 117120 LUTs, 234240 FFs, and 23.06 Mb of on-chip memory (combining BRAM and URAM).\u003c/p\u003e\n\u003cp\u003eThis makes the board, arguably, the most cost-effective board. For example, if we compare the LUTs per dollar, FFs per dollar, and on-chip memory per dollar, it is one of the cheapest boards out there, as it can be seen on \u003ca href=\"#tab-cost-effective\"\u003eTable 1\u003c/a\u003e.\u003c/p\u003e","title":"Adding an External Clock to the KV260 Dev Board"}]